AI Chips and Photonics Raise New Challenges for Thermal Design

Thermal design for AI systems gets harder when a package combines processors, memory and photonics: each responds to heat on a different timescale, and the resulting stress can shift optical behavior as well as chip performance. The panel discussion below points to a practical need: model those interactions early, across the full assembly, and account for workloads that fluctuate over time.

That need is becoming more pressing as designers pursue higher bandwidth through stacked dies and co-packaged optics. Photonics may help move data with less energy, but integrating it brings thermal sensitivity, control complexity and mechanical effects that conventional electronic models may not capture. The speakers also identified a gap in tools for predicting how heat accelerates aging.

Photonics brings heat and stress into the design

Chris Mueth, director of new markets management at Keysight EDA, said photonics has potential to ease data center bottlenecks, but scaling a large mesh switch remains difficult. Such a system can require many components and suffer high losses. In his view, broader adoption depends on rethinking the architecture around modular designs that can scale.

Heat adds a second challenge. Photonic structures are sensitive to temperature, and they use heaters to tune and stabilize their operation. A large switch could require thousands of heaters, Mueth said, making calibration and control a substantial task. Solving that would help, though it would not eliminate losses in the photonics chips themselves.

Co-packaged optics brings silicon photonics closer to electronic integrated circuits (EICs), alongside photonic integrated circuits (PICs). Satish Radhakrishnan, head of semiconductor and electronics at Vinci, said this arrangement aims to keep the components compact and thermally isolated. But the package’s behavior changes over time: heat from one device may take time to reach another, lingering as a later burst of activity begins.

That timing matters because even a small temperature change can shift a ring oscillator, Radhakrishnan said. He argued that designers need to simulate the complete system in a transient domain, tracking changes over time rather than relying only on a static thermal picture. That analysis would help establish whether co-packaged optics can operate reliably alongside the electronics.

Placement can complicate the picture further. The electronic driver for a co-packaged optical system may sit near or above the PIC, bringing heat close to temperature-sensitive optical structures. Mueth said that arrangement can introduce mechanical stress with a significant effect on optical signals, potentially greater than the thermal effect itself. Moving components can therefore improve one aspect of the design while making another worse.

Lang Lin, director of product management at Synopsys, described silicon photonics as closer to an analog circuit than a digital one in its thermal behavior. Digital transistors switch, while analog devices can draw direct current continuously. Current through interconnects generates heat; in co-packaged optics, some heat is also needed to operate the electronic components. The design challenge is to position heaters and other elements so they can work without creating damaging hot spots or stress.

Sensing and calibration add their own complexity. Mueth said designers can place a monitoring loop inside a PIC as part of calibration, but that increases the system’s complexity. A sensor plan needs to show that measurements remain useful across the device, not simply that sensors are present.

Warpage and workload timing require broader models

Heat can warp dies, and thinning them to flatten a package may affect how well it dissipates heat. Jack Berg, vice president of business development at Silvaco, said thermal variation can cause more feature mismatch in a PIC than in electronic integrated circuits. Photonics is also sensitive to warpage and thermal gradients, while a laser can act as a heat source with reliability implications.

That makes the modeling problem multi-physics. Berg said photonics design may require electrical, mechanical, thermal and optical analysis together. Traditional semiconductor analysis often gave less attention to passive components; photonics makes their thermal behavior harder to ignore. In Berg’s assessment, the field’s long development reflects how many interacting physical effects it must account for.

These interactions matter in multi-die packages built to meet the performance demands of AI systems. Chris Mueth said teams should model high-performance workloads during architecture work, including their thermal, electrical and mechanical effects. That early analysis can reveal problems before the design is further along, when changes are more difficult.

Running separate analyses can miss how the system behaves as a whole. John Ferguson, senior director of product management at Siemens EDA, said designers may need to run thermal, electrical and mechanical models repeatedly in sequence until the system reaches a steady condition. Even then, the result depends on the design and the conditions being modeled.

Transient analysis can also clarify how much power a chip can use for short bursts. Radhakrishnan said designers need to consider both the duration of a high-power event and how often it repeats. A nanosecond burst occurring frequently may affect temperatures differently from one that is rare. Understanding those patterns could help teams balance peak performance against the package’s thermal limits.

That is especially relevant as AI hardware evolves to support both training and inference, with bandwidth demands contributing to stacked designs. Radhakrishnan’s point was that peak performance alone does not describe the workload: engineers need to understand how often high-power periods occur and how long the system has to cool between them.

Shared models could make package analysis practical

Simulating a complete multi-die system requires models that can be assembled across components and suppliers. Lin described a possible flow in which a high-bandwidth memory vendor provides a model to a system integration company. The integrator then combines it with models for other components, builds a representation of the stack and analyzes the complete package.

Hierarchical models are useful for managing the scale of the simulation, but they also depend on cooperation across the supply chain. Lin said vendors and integrators need agreed standards for sharing models so the pieces can be connected consistently. Without that coordination, system-level analysis becomes harder to assemble and interpret.

This is a design workflow issue as much as a software issue. Component suppliers need to provide models that preserve the behavior relevant to the full package, while integrators need to combine them and examine interactions across the stack. The panel described this shared approach as necessary for analyzing increasingly complex systems.

Aging remains a weak spot

Heat also speeds degradation in data paths through mechanisms such as electromigration. Radhakrishnan said some designs embed thermal sensors in the die to monitor aging. Software can use the sensor data to identify changes and throttle selected regions, but engineers first need to determine whether sensors are in the right locations and provide useful readings as conditions change.

Long-lived devices make that question particularly demanding. Radhakrishnan cited automotive chips, which may need to last 10 to 15 years, as a case where designers must account for how performance changes over time. Ambient temperature matters too. Berg pointed to the Arrhenius equation as a common way to frame temperature’s effect on reliability, emphasizing that relatively small temperature differences can have substantial consequences.

Lin said tools for accurately predicting thermally induced aging are still lacking. Sensors can help track degradation once a chip is operating, but they do not solve the design problem of predicting aging or optimizing the design around it. Radhakrishnan described the underlying tension as a balance between under-design and over-design, with conditions changing over the device’s lifetime.

The near-term engineering takeaway is clear: teams need thermal analysis that follows time, captures mechanical and optical effects, and connects component models into a package-level view. Better aging prediction remains an open tool gap. For photonics and stacked AI systems, those capabilities will help determine whether a design’s performance holds up outside its peak operating case.

Experts at the Table: Semiconductor Engineering held the discussion at the recent Design Automation Conference with Lang Lin of Synopsys; Jack Berg of Silvaco; Satish Radhakrishnan of Vinci; Chris Mueth of Keysight EDA; and John Ferguson of Siemens EDA. This is the second installment in a three-part series.

L-R: Silvaco’s Berg; Synopsys’ Lin; Vinci’s Radhakrishnan; Keysight’s Mueth; Siemens’ Ferguson.

Read the first discussion:
Scaling Thermal Analysis From Transistors To Data Centers
Rising power density and chiplet complexity bring thermal analysis earlier into design.

Related:
Photonics Fundamentals For Electronics Engineers: eBook

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