TSMC’s Reported CoWoS Price Increase Puts AI Packaging Costs in Focus

Advanced packaging is becoming a more expensive constraint in the AI chip supply chain. TSMC is reportedly considering raising prices for its Chip on Wafer on Substrate (CoWoS) technology by as much as 20%, according to Trendforce, citing supply chain sources and local media. TSMC hasn’t confirmed the reported increase, so its timing and final size remain open questions. Still, the possibility shows how costs can rise at a packaging stage that AI accelerators depend on as much as they depend on advanced silicon.

CoWoS brings logic dies and high-bandwidth memory (HBM) stacks together in one package. That close integration gives accelerators the data bandwidth their workloads require, but it also makes production more demanding as designers add compute and memory. Nvidia’s Blackwell combines two large GPU dies with eight HBM3E stacks. Upcoming Rubin and Rubin Ultra products are expected to push integration further, which may add pressure to packaging capacity and the suppliers that support it. Substrates and other packaging materials are part of that broader supply chain.

More complex chips take longer to clear testing

The package itself is only part of the capacity challenge. Testing can keep equipment occupied for longer as chip designs grow more complex. Blackwell reportedly takes three to four times as long to test as Nvidia’s previous-generation Hopper, while Rubin could require as much as seven times longer. These figures are reports, but the operational effect is straightforward: if each package spends more time in testing, a facility needs more test capacity to process the same volume.

That leaves manufacturers with several linked constraints. More compute and memory make packages harder to build; longer test cycles tie up equipment; and demand for AI systems gives customers a reason to seek more production. Server CPUs and custom ASICs also use advanced packaging, so accelerator makers aren’t the only customers drawing on capacity. For teams planning hardware launches, a wafer supply commitment alone may not settle the question of when finished processors will be available.

Equipment availability adds another complication. Reported delivery times for chipmaking tools have stretched from three to six months to as long as eight months. Trendforce’s account says TSMC placed this year’s equipment orders at existing prices instead of negotiating for discounts or added features, a shift from its customary purchasing approach. The reported choice suggests that, under tight supply, securing a delivery slot can matter more than improving the purchase terms.

The scale of the equipment push has also changed quickly. A September report said TSMC’s projected semiconductor equipment requirements had nearly doubled in six months. By July, deputy co-COO Cliff Hou said expected needs had reached 1.9 times the company’s original estimate as AI demand accelerated. “Compared with the pattern 30 years ago, we have never seen the demand increase that much, that frequency of changes,” Hou said at the time. That jump helps explain why adding capacity involves more than deciding to buy tools: the tools themselves need to arrive, be installed and support production.

More suppliers help, but don’t remove the bottleneck

TSMC is working to widen its packaging supply chain. Earlier this month, GlobalFoundries agreed to make silicon interposers for TSMC’s CoWoS under a five-year contract valued at $2 billion. Production is expected to ramp up in the first half of 2028. That arrangement adds a source for one packaging component, but interposers are only one part of the process. It can ease pressure on that step without resolving constraints elsewhere in packaging, testing or equipment supply.

CoWoS pricing is also part of a wider set of reported cost increases. TSMC is reportedly considering raising prices for 2027, with advanced process wafer prices expected to rise by 5% to 10%. Customers using 2nm and 3nm-class processes could face the steepest increases. Those seeking capacity beyond their original allocations may pay extra premiums, with some costs potentially rising by as much as 25%. These figures are not confirmed company pricing, and actual effects will depend on customer agreements and product requirements.

Industry estimates cited by Trendforce put TSMC’s monthly capacity above 106,000 wafers in 2026, with a target of 227,000 in 2027. Those wafer figures describe one part of the production picture; they don’t show how quickly complex packages can move through every later step. If both the reported wafer and CoWoS increases materialize, AI hardware makers will face higher input costs, with some likely passed along to customers.

For product and infrastructure teams, the practical question is whether added capacity arrives in time to match planned chip volumes. The GlobalFoundries interposer ramp is set for 2028, while equipment delivery delays and longer test cycles affect nearer-term output. The next useful signals will be confirmation of TSMC’s pricing plans, progress on packaging capacity and evidence that testing throughput is keeping pace with more complex designs.

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