Autonomous Chip Design Advances From RTL Generation Toward Full Workflow Orchestration

AI systems can now take some chip projects from a customer’s specification to verified RTL, according to Synopsys CEO Sassine Ghazi. That’s a meaningful step toward autonomous chip design, but it doesn’t yet cover the full path to a manufactured part. Physical implementation, verification and final approval remain ahead, while human engineers still define architectures and judge whether a design is ready.

That gap matters because chip development is being asked to move at the pace of changing AI workloads. Ghazi says system companies want custom silicon on schedules shorter than a year, while AI models can change every three to four months. The challenge is no longer just optimizing a chip in isolation. Teams must connect the workload to the software, architecture, materials, manufacturing process, package and physical behavior of the finished system.

Ghazi discussed these changes in a live interview with Semiconductor Engineering at SEMICON West. His account offers a view of where AI assistance is already being used, what remains difficult, and why design automation increasingly has to account for physics beyond the chip.

From design assistance to coordinated agents

Synopsys began using reinforcement learning in some tools around 2016, Ghazi said. The aim was to help engineers navigate large sets of design parameters and improve a chosen outcome. The newer approach he describes moves beyond a single assistant: more than 40 task agents are configured as experts in particular tools and tasks, with relevant tool knowledge and capabilities.

The shift depends on advances in models’ reasoning and their ability to plan over longer sequences. Instead of asking for help with one step, an engineer can describe an outcome and have a model coordinate multiple agents to pursue it. Ghazi calls this autonomous engineering. In practice, the agents still depend on the underlying design tools to generate and validate results; the model’s role is to reason, explore options and coordinate work.

That distinction helps clarify whether agents replace EDA tools or become a new form of design IP. Ghazi’s answer is that both the tools and the agents matter. A model can examine possibilities, but producing and checking an implementation requires specialized software and agents that know how to use it. The final design also has to be selected against competing goals such as performance, power and cost.

Customization extends to interface IP, which connects chips to each other and to the larger system. General-purpose interfaces may leave performance or area on the table when a system company is tailoring a chip for a specific workload. Ghazi argues that such customers increasingly need interface IP adapted to their design targets. That makes the design flow’s ability to accommodate specific requirements part of the competitive equation.

Autonomy has reached RTL, not the factory gate

One active use case begins with a system company’s specification. The customer describes what an end product needs; that information must then be translated into an electronic specification and, eventually, a chip design. Ghazi says Synopsys has customer engagements in which its Autonomous Agent can take a specification through to verified RTL—the hardware description that forms a starting point for chip design.

That step previously involved engineers translating the specification, writing RTL, verifying it and checking whether it could be physically implemented and manufactured. Automating the work can shorten a labor-intensive stage and help address a shortage of engineers who can architect silicon and carry a project from requirements toward a working part.

But verified RTL is not the same as a completed chip. Ghazi says extending autonomy into physical implementation, physical verification and chip sign-off remains an ambition. He expects the workflow to expand, but says those later stages are not autonomous today. There is also a human role before manufacturing: setting the architecture, providing direction and making the final judgment about whether the design is ready.

Some chipmakers have described a goal of developing chips without a person involved in the process. Ghazi treats that as an ambition rather than a present capability. The gap between an automated specification-to-RTL flow and a fully validated physical design is substantial. For engineering teams, the practical question is which stages can be automated reliably, how much review each stage needs, and whether the resulting schedule gains hold up across real projects.

The tools also have to resolve trade-offs, not merely produce a plausible design. A chip that wins on one measure may lose on another, and its suitability depends on the workload and the system around it. Human judgment remains part of defining those priorities and deciding which candidate should advance.

Physical AI widens the design problem

As AI moves from digital services into vehicles, robots and other physical products, silicon is only one piece of the engineering task. Ghazi describes a need to co-design the chip, the software, the mechanical system and the environment in which the product operates. For an autonomous vehicle, for example, the system has to be evaluated as electronics working within a physical structure and under real operating conditions.

This calls for simulation across several kinds of physics. Engineers need to understand how the electronic design interacts with heat, materials, structure and fluid behavior, and whether the combined product is built with the right amount of capacity. Ghazi says Synopsys’ acquisition of Ansys expanded its work from silicon into system-level analysis and multiphysics sign-off.

The word “system” changes meaning as designs are viewed at different scales. An advanced package can be treated as a system in its own right, then as a component within a rack, a subsystem or a data center. That nested structure makes analysis harder: a decision that appears sound for one component may affect behavior elsewhere. Co-design has to follow the product across those levels.

Digital twins can help by letting teams test designs in software before committing to physical builds. Ghazi says Synopsys made two acquisitions about 15 or 17 years ago focused on virtualizing chips, so customers could begin software development before a chip was manufactured and compare which chip model best fit their system.

Customers also use digital representations for parts of larger products. Ghazi describes work involving a vehicle’s electronics and virtual crash testing of its structure and materials, which can reduce reliance on physical prototypes for those evaluations. Yet he says a widely used twin that combines electronics, physics and the operating environment into one model is not yet available. He expects that kind of capability to become necessary for sophisticated intelligent systems, in part because building and testing every version physically would take too long and cost too much.

Some newer companies can start with a fully digital design process, Ghazi said, pointing to robotics and electric vehicle companies in China. He described teams that began from scratch, completed a silicon tape-out, installed the chip in a board and then in an end product, with software running within weeks. He contrasted that pace with established automakers, which traditionally create a new vehicle platform every four to six years. In the examples he cited, newer companies update the electronics and vehicle on a cycle of roughly nine months to a year.

That faster cycle requires substantial computing resources. The potential payoff, Ghazi argues, is a more differentiated product and a quicker pace of development. Established companies face a harder transition: they need to change engineering workflows while still meeting existing customer commitments. Starting with a clean design and organization may make a fully digital approach easier than adapting a large, established operation.

3D chip designs bring heat and mechanics into focus

Ghazi says 3D integrated circuits are already present in data centers, though their adoption brings challenges beyond circuit architecture. In stacked designs, intense workloads can create heat within the package. The resulting mechanical stress can warp or crack chiplets, making thermal and structural behavior a design concern from the outset.

That’s why teams need to consider the workload while planning the package and the multi-die system. A workload can produce bursts of activity that create thermal conditions a design team didn’t anticipate. If those corner cases emerge only after deployment, the system may overheat or fail. The analysis therefore needs to connect software behavior with package architecture, implementation and physical simulation.

Ghazi links this need to Synopsys’ acquisition of Ansys: bringing physics simulation earlier into design can help teams identify mechanical and thermal problems before manufacturing. His broader point is that heterogeneous integration—combining multiple chips—raises the value of analyzing electronics and physical effects together.

The workload itself is also a moving target. As AI models and the complexity of their queries change, a chip tuned to yesterday’s demands can become a poor match. Ghazi says models are changing every three to four months, while a silicon refresh has traditionally taken years. Semiconductor companies are trying to bring development cycles down from 18, 16 or 14 months toward a year. System companies want to use AI to cut the specification-to-tape-out process to less than a year, and in some cases less than nine months.

That pressure helps explain why more system companies want control over silicon development. Their aim is to define chips around the workloads they expect to run, then update them as those workloads change. Programmable chips or chiplets could offer another way to adapt, but Ghazi says system companies are currently more focused on speeding up specification and customization. He also notes that custom silicon may serve an application for only two to three years, reducing the need to make each design fit several generations of models.

Speed is the opportunity and the strain

Ghazi’s main concern is the pace of change. The industry is taking on more system-level complexity while trying to deliver current projects and transform how engineering gets done. A new workflow can look straightforward in a presentation; putting it into practice means changing how teams combine AI, physics and product requirements without missing existing commitments.

That transformation also affects investment. EDA companies have long devoted a large share of revenue to research and development, Ghazi said. He sees opportunities for AI to improve engineering, but says it has not yet reduced the investment needed to keep up. Synopsys’ spending, in his account, continues to rise.

The near-term measure of progress, then, is not whether every engineer disappears from chip design. It’s whether autonomous agents can reliably take on more of the work between a product requirement and a manufacturable, physically validated design. Verified RTL shows that parts of the journey are already being automated. The next test is whether those gains extend through physical implementation and sign-off, while keeping pace with workloads that change faster than silicon can be rebuilt.